This is a Divisional of application Ser. No. 09/716,012 filed Nov. 18, 2000, now abandoned.
The present application also contains subject matter related to co-pending U.S. patent application Ser. No. 10/197,067 by Kashmir S. Sahota, Kai Yang, and Steven C. Avanzino entitled xe2x80x9cCONDUCTOR CHEMICAL-MECHANICAL POLISHING IN INTEGRATED CIRCUIT INTERCONNECTSxe2x80x9d, which is a divisional of U.S. patent application Ser. No. 09/715,670, now abandoned.
The present invention relates generally to semiconductor technology and more specifically to chemical-mechanical polishing solutions and pads in semiconductor processing.
In the manufacture of integrated circuits, after the individual devices such as the transistors have been fabricated in and on the semiconductor substrate, they must be connected together to perform the desired circuit functions. This interconnection process is generally called xe2x80x9cmetallizationxe2x80x9d and is performed using a number of different photolithographic, deposition, and removal techniques.
In one interconnection process, which is called a xe2x80x9cdual damascenexe2x80x9d technique, two channels of conductor materials are separated by interlayer dielectric layers in vertically separated planes perpendicular to each other and interconnected by a vertical connection, or xe2x80x9cviaxe2x80x9d, at their closest point. The dual damascene technique is performed over the individual devices which are in a device dielectric layer with the gate and source/drain contacts, extending up through the device dielectric layer to contact one or more channels in a first channel dielectric layer.
The first channel formation of the dual damascene process starts with the deposition of a thin first channel stop layer. The first channel stop layer is an etch stop layer which is subject to a photolithographic processing step which involves deposition, patterning, exposure, and development of a photoresist, and an anisotropic etching step through the patterned photoresist to provide openings to the device contacts. The photoresist is then stripped. A first channel dielectric layer is formed on the first channel stop layer. Where the first channel dielectric layer is of an oxide material, such as silicon oxide (SiO2), the first channel stop layer is a nitride, such as silicon nitride (SiN), so the two layers can be selectively etched.
The first channel dielectric layer is then subject to further photolithographic process and etching steps to form first channel openings in the pattern of the first channels. The photoresist is then stripped.
An optional thin adhesion layer is deposited on the first channel dielectric layer and lines the first channel openings to ensure good adhesion of subsequently deposited material to the first channel dielectric layer. Adhesion layers for copper (Cu) conductor materials are composed of materials such as tantalum (Ta), titanium (Ti), tungsten (W), and their nitrides which are good barrier materials and have good adhesion to the dielectric materials.
Good barrier materials provide resistance to the diffusion of copper from the copper conductor materials to the dielectric material. High barrier resistance is necessary with conductor materials such as copper to prevent diffusion of subsequently deposited copper into the dielectric layer, which can cause short circuits in the integrated circuit.
However, these nitride compounds also have relatively poor adhesion to copper and relatively high electrical resistance.
Because of the drawbacks, pure refractory metals such as tantalum (Ta), titanium (Ti), or tungsten (W) are deposited on the adhesion layer to line the adhesion layer in the first channel openings. The refractory metals are good barrier materials, have lower electrical resistance than their nitrides, and have good adhesion to copper.
In some cases, the barrier material has sufficient adhesion to the dielectric material that the adhesion layer is not required, and in other cases, the adhesion and barrier material become integral. The adhesion and barrier layers are often collectively referred to as a xe2x80x9cbarrierxe2x80x9d layer herein.
For conductor materials such as copper, which are deposited by electroplating, a seed layer is deposited on the barrier layer and lines the barrier layer in the first channel openings. The seed layer, generally of copper, is deposited to act as an electrode for the electroplating process.
A first conductor material is deposited on the seed layer and fills the first channel opening. The first conductor material and the seed layer generally become integral, and are often collectively referred to as the conductor core when discussing the main current-carrying portion of the channels.
A chemical-mechanical polishing (CMP) process is then used to remove the first conductor material, the seed layer, and the barrier layer above the first channel dielectric layer to form the first channels. When a layer is placed over the first channels as a final layer, it is called a xe2x80x9ccappingxe2x80x9d layer and the xe2x80x9csinglexe2x80x9d damascene process is completed. When additional layers of material are to be deposited for the dual damascene process, the capping layer also functions as an etch stop layer for a via formation step.
The via formation step of the dual damascene process continues with the deposition of a via dielectric layer over the first channels, the first channel dielectric layer, and the capping or via stop layer. The via stop layer is an etch stop layer which is subject to photolithographic processing and anisotropic etching steps to provide openings to the first channels. The photoresist is then stripped.
A via dielectric layer is formed on the via stop layer. Again, where the via dielectric layer is of an oxide material, such as silicon oxide, the via stop layer is a nitride, such as silicon nitride, so the two layers can be selectively etched. The via dielectric layer is then subject to further photolithographic process and etching steps to form the pattern of the vias. The photoresist is then stripped.
A second channel dielectric layer is formed on the via dielectric layer. Again, where the second channel dielectric layer is of an oxide material, such as silicon oxide, the via stop layer is a nitride, such as silicon nitride, so the two layers can be selectively etched. The second channel dielectric layer is then subject to further photolithographic process and etching steps to simultaneously form second channel and via openings in the pattern of the second channels and the vias. The photoresist is then stripped.
An optional thin adhesion layer is deposited on the second channel dielectric layer and lines the second channel and the via openings.
A barrier layer is then deposited on the adhesion layer and lines the adhesion layer in the second channel openings and the vias.
Again, for conductor materials such as copper and copper alloys, which are deposited by electroplating, a seed layer is deposited by electro-less deposition on the barrier layer and lines the barrier layer in the second channel openings and the vias.
A second conductor material is deposited on the seed layer and fills the second channel openings and the vias.
A CMP process is then used to remove the second conductor material, the seed layer, and the barrier layer above the second channel dielectric layer to simultaneously form the vias and the second channels. When a layer is placed over the second channels as a final layer, it is called a xe2x80x9ccappingxe2x80x9d layer and the xe2x80x9cdualxe2x80x9d damascene process is completed.
Individual and multiple levels of single and dual damascene structures can be formed for single and multiple levels of channels and vias which are collectively referred to as xe2x80x9cinterconnectsxe2x80x9d.
The use of the single and dual damascene techniques eliminates metal etch and dielectric gap fill steps typically used in the metallization process. The elimination of metal etch steps is important as the semiconductor industry moves from aluminum (Al) to other metallization materials, such as copper, which are very difficult to etch.
One of the major problems encountered during the CMP process is that the various solutions used to provide the chemical portion of the process do not have high selectivity from the conductor material, such as copper (Cu) to the barrier materials, such as tantalum (Ta) or tantalum nitride (TaN). The current selectivity is in the range of 20:1 selectivity of copper to tantalum or tantalum nitride.
As a result of the lack of high selectivity to the barrier material, when the barrier layer is polished away, both the channels and dielectric layers are subject to xe2x80x9cerosionxe2x80x9d, or undesirable CMP of the channel and dielectric materials, which makes it difficult to control the channel thickness.
Also, because of the lack of high selectivity to the barrier material, when the barrier layer is polished away, the channels alone are subject to xe2x80x9cdishingxe2x80x9d, or undesirable CMP of the conductor material, which also makes it difficult to control the channel thickness.
One problematic answer to this problem has been to provide very thick barrier layers, which provide large process margins during CMP. Unfortunately, these materials have relatively high resistance and tend to reduce the overall current-carrying capability of the channels.
Solutions to these problems have been long sought but have long eluded those skilled in the art.
The present invention provides an integrated circuit having a semiconductor substrate with a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. A barrier layer lines the opening, and a conductor material fills the opening over the barrier layer. By using a polishing solution having a high selectivity from the barrier layer to the dielectric layer, a very thin barrier layer may be used without causing the channels and the dielectric layer to be subject to conventional erosion or the channels being subject to conventional dishing. As a result, improved channel thickness control is achieved and the conductivity of the channel is improved.
The present invention further provides a method for manufacturing an integrated circuit having a semiconductor substrate with a semiconductor device. A dielectric layer is formed on the semiconductor substrate and an opening is formed in the dielectric layer. A barrier layer is deposited to line the opening and conductor core is deposited to fill the channel opening over the barrier layer. By using a polishing solution having a high selectivity from the barrier layer to the dielectric layer, a very thin barrier layer may be used without causing the channels and the dielectric layer to be subject to conventional erosion or the channels being subject to conventional dishing. As a result, improved process margins are achieved.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.